View TSSOP-28_4548617.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

unisonic technologies co., ltd m1008 preliminary cmos ic www.unisonic.com.tw 1 of 11 copyright ? 2010 unisonic technologies co., ltd qw-r502-434.a 16-bit ccd/cis analog signal processor ? description the m1008 is a 16-bit ccd/cis analog signal processor for imaging applications. a 3-channel architecture is designed to sample and control the outputs of tri-linear color ccd arrays. each channel processes one color analog signal and includes an input clamp, correlated double sampler (cds), offset dac and programmable gain amplifier (pga), and a 16-bit a/d converter. if there are sensors such as contact image sensors (cis) and cmos active pixel sensors, the cds amplifiers are not necessary. the 16-bit digital output is composed of high and low 8-bit output and is assessed by two reading cycles. the internal registers are programmed by a 3-wire serial interface which provides gain, offset and operating mode adjustments. the typical operation power of m1008 is 400mw in 5v power supply. ? features * 400mw in 5v operation supply * under 2ma power-down mode * built-in16-bit 30 msps a/d converter * no missing codes * input clamp circuitry * correlated double sampling * programmable gain * 250mv programmable offset * built-in voltage reference * programmable 3-wire serial interface * 3v/5v digital i/o compatibility * up to 25 msps in 1-channel operation * up to 30 msps in 2-channel (even-odd) operation * up to 30 msps in 3-channel operation ? ordering information ordering number package packing m1008g-p28-t TSSOP-28 tube m1008g-p28-r TSSOP-28 tape reel m1008g -p28 -t (1) packing type (2) package type (3) halogen free (1) t: tube, r: tape reel (2) p28: TSSOP-28 (3) g: halogen free TSSOP-28
m1008 preliminary cmos ic unisonic technologies co., ltd 2 of 11 www.unisonic.com.tw qw-r502-434.a ? pin configurations ? pin description pin no. pin name pin type pin description 1 cdsclk1 di cds reference clock pulse input 2 cdsclk2 di cds data clock pulse input 3 adcclk di a/d sample clock input for 3-channels mode 4 oe di output enable, active low 5 drv dd p digital driver power 6 drv ss p digital driver ground 7~14 d7~d0 do digital data output 15 sdata di/do serial data input/output 16 sclk di clock input for serial interface 17 sload di serial interface load pulse 18,28 av dd p analog supply 19,27 av ss p analog ground 20 refb ao reference decoupling 21 reft ao reference decoupling 22 vinb ai analog input, blue 23 cml ao internal reference output 24 ving ai analog input, green 25 offset ao clamp bias level decoupling 26 vinr ai analog input, red note: i=input, o=outpu t, i/o=input/output, p=power supply, g=ground
m1008 preliminary cmos ic unisonic technologies co., ltd 3 of 11 www.unisonic.com.tw qw-r502-434.a ? block diagram
m1008 preliminary cmos ic unisonic technologies co., ltd 4 of 11 www.unisonic.com.tw qw-r502-434.a ? absolute maximum rating parameter symbol ratings unit supply voltage v dd v ss -0.3 to v ss +5.5 v input voltage v in v ss -0.3 to v dd +0.3 v ambient operation temperature t opr -25 ~ +75 c storage temperature t stg -50 ~ +125 c note: absolute maximum ratings are those values be yond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device oper ation is not implied. ? electrical characteristics (av dd =5v, dv dd =3v, t a =25c. unless otherwise specified) parameter symbol test condition min typ max unit analog power supply v add 4.75 5 5.25 v digital power supply v drdd 3 5 5.25 v 3-channel mode with cds t max3 30 msps 2-channel mode with cds t max2 30 msps 1-channel mode with cds t max1 25 msps adc resolution 16 bits integral nonlinear (inl) 32 lsb differential nonlinear (dnl) -1 1 lsb offset error -100 100 mv gain error 5 %fsr full-scale input range r fs 2.0 v p-p input limits v i(limit) a vss -0.3 5 a vdd +0.3 v input current i in 10 na pga gain at minimum 1 v/v pga gain at maximum 5.85 v/v pga gain resolution 6 bits programmable offset at minimum -250 mv programmable offset at maximum 250 mv offset resolution 9 bits operating t a 0 70 c total power consumption p tot 400 mw high level input voltage (cdsclk1, cdsclk2, adcclk, oe , sck, sload) v ih 0.8*v dd v low level input voltage (cdsclk1, cdsclk2, adcclk, oe , sck, sload) v il 0.2*v dd v high level input voltage (sdata) v ih1 0.8*v dd v low level input voltage (sdata) v il1 0.2*v dd v high level input current i ih 10 ua low level input current i il 10 ua input capacitance c in 10 pf high level output voltage (sdata, d0~d7) v oh v dd -0.5 v low level output voltage (sdata, d0~d7) v ol 0.5 v high level output current i oh 1 ma low level output current i ol 1 ma
m1008 preliminary cmos ic unisonic technologies co., ltd 5 of 11 www.unisonic.com.tw qw-r502-434.a ? timing specification parameter symbol test condition min typ max unit 3-channel pixel rate t pra 100 ns 2-channel pixel rate t prb 66 ns 1-channel pixel rate t prc 40 ns adcclk pulse width t adclk 16 ns cdsclk1 pulse width t c1 12 ns cdsclk2 pulse width t c2 12 ns cdsclk1 falling to cdsclk2 rising t c1c2 0 ns adcclk rising to cdsclk1 falling t adc1 0 ns adcclk rising to cdsclk2 falling t adc2 0 ns analog sampling delay t ad 5 ns 3-channel mode only cdsclk2 falling to cdsclk1 rising ta c2c1 30 ns cdsclk2 falling to adcclk rising ta c2adr 30 ns 2-channel mode only cdsclk2 falling to adcclk rising tb c2adr 30 ns cdsclk1 rising to adcclk rising tb c1adr 15 ns cdsclk2 falling to cdsclk1 rising tb c2c1 15 ns 1-channel mode only cdsclk2 falling to adcclk rising tc c2adr 20 ns cdsclk1 rising to adcclk falling tc c1adf 0 ns cdsclk2 falling to cdsclk1 rising tc c2c1 15 ns serial interface maximum sclk frequency f sclk 10 mhz sload to sclk setup time t ls 10 ns sclk to sload hold time t lh 10 ns sdata to sclk rising setup time t ds 10 ns sclk rising to sdara hold time t dh 10 ns falling to sdata valid t rdv 10 ns data output output delay t od 8 ns latency(pipeline delay) 9 cycles
m1008 preliminary cmos ic unisonic technologies co., ltd 6 of 11 www.unisonic.com.tw qw-r502-434.a ? functional description offset error at a level of 1/2 lsb above the nominal zero scale vo ltage, the first adc code transition should come. the offset error is defined as the deviation between the ac tual first code transition level with the ideal level. gain error at a level of 1/2 lsb below the nominal full-scale voltage, the last code transition should come. gain error is defined as the deviation of the actual difference between the first and the last code transitions and the ideal difference between the first and the last code transitions. internal register descriptions address data bits register name a2 a1 a0 d8 d7 d6 d5 d4 d3 d2 d1 d0 configuration 0 0 0 0 0 1 3-ch cds on clamp voltage enable power down output delay 1 byte out mux 0 0 1 0 rgb/ bgr red green blue delay enable cdsclk1 delay cdsclk 2 delay adcclk delay red pga 0 1 0 0 0 0 msb lsb green pga 0 1 1 0 0 0 msb lsb blue pga 1 0 0 0 0 0 msb lsb red offset 1 0 1 msb lsb green offset 1 1 0 msb lsb blue offset 1 1 1 msb lsb internal register map configuration register the configuration register sets the m1008 ?s operating mode and bias levels. bits d6 should always hold high. bit d5 configures the m1008 for the 3-channel(high) operation mode. bit d4 will be set high to implement the cds mode operation, and be set low to im plement the sha mode operation. bit d3 controls the dc bias level of the m1008 ?s input clamp. this bit should hold high for the 4v clamp bias, unless a ccd with a reset feed through transient exceeding 2v is applied. the clamp voltage is 3v with this bit low. bit d2 controls the power-down mode. with bit d2 high, the m1008 will come to a very low power ?sleep? mode, in which all register contents are retained. bit d1 is se t high for the digital output (d0~d7) delay 2ns. bit d0 configures the out put mode of the m1008 . setting the bit high can implement a single byte output mode in which only one byte of the 16b adc is output. inversely, the 16b adc output is multiplexed into two bytes. d8 d7 d6 d5 d4 d3 d2 d1 d0 3-channels cds operation clamp bias power-down output delay high byte out 1=on (note) 1=cds mode (note) 1=4v (note) 1=on 1=on 1=on 0 0 1 0=off 0=sha mode 0=3v 0=off (note) 0=off (note) 0=off configuration register settings note: power-on default value mux register the sampling channel order and 2-ch annel mode configuration in the m1008 are both controlled by the mux register. bits d8 should hold low. bit d7 goes into effect in the 3-channel mode or the 2-channel mode of operation. setting it high will sequence the mux to sample the red channel first, then the green channel, and the last blue channel. in the 3-channel mode, the cdsclk2 rising edge al ways resets the mux to sample the red channel first (see timing diagrams). when bit d7 is set low, the channel order is reversed to blue first, green second, and red third, the cdsclk2 rising edge will always reset the mux to sample the blue channel first. bits d6, d5, and d4 go into effect when operating in 1 or 2-channel mode. bit d6 is set high to sample the red channel. bit d5 is set high to sample the green channel. bit d4 is set high to sample the blue channel. the mux remains stationary during 1-channel mode . setting two of bits d4~d6 high to configure the two channel mode, and the sequence of sampling is selected by bit d7. bits d0~d3 are applied to controlling cdsclk1, cdsclk2 and adcclk internal delay.
m1008 preliminary cmos ic unisonic technologies co., ltd 7 of 11 www.unisonic.com.tw qw-r502-434.a ? functional description (cont.) d8 d7 d6 d5 d4 d3 d2 d1 d0 mux order channel select enable delay cds1 delay cds2 delay adck delay 1=on (note) 1=4ns 1=4ns 1=2ns 0 1=r-g-b (note) 0=b-g-r 1=red (note) 0=off 1=green 0=off (note) 1=blue 0=off (note) 0=off 0=2ns (note) 0=2ns (note) 0=0ns (note) mux register settings note: power-on default value pga gain registers there are three pga registers for use in respecti vely programming the gain of the red, green and blue channels. bits d8, d7 and d6 in each register must hold lo w, and bits d5 through d0 control the gain range in 64 increments. the coding for the pga regist ers is a straight binary. an all zero word corresponds to the minimum gain setting (1x) and an all one word corresponds to the maximum gain setting (5.85x). the m1008 distributes one programmable gain amplifier (p ga) for each channel. each pga has a gain range from 1x (0db) to 5.85x (15.3db), adjustable in 64 steps. al though the gain curve is appr oximately linear in db, the gain in v/v varies in nonlinear proportion with the regi ster code, according to t he following the equation: 5.85 gain 63 - g 1 + 4.85 * ( ) 63 = where g is the decimal value of the gain re gister contents, and varies from 0 to 63. d8 d7 d6 d5 d4 d3 d2 d1 d0 gain(v/v) gain(db) 0 0 0 msb lsb 0 0 . . . 0 0 0 0 . . . 0 0 0 0 . . . 0 0 0 0 . . . 1 1 0 0 . . . 1 1 0 0 . . . 1 1 0 0 . . . 1 1 0 0 . . . 1 1 0 (note) 1 . . . 0 1 1.0 1.013 . . . 5.43 5.85 0.0 0.12 . . . 14.7 15.3 note: power-on default value offset registers there are three pga registers for use in respectively programming the offset of the red, green, and blue channels. bits d8 through d0 control the offs et range from -250mv to 250mv in 512 increments. the coding for the offset registers is sign magnitude, with d8 as the sign bit. the following table shows the offset range as a function of the bits d8 through d0. d8 d7 d6 d5 d4 d3 d2 d1 d0 offset(mv) msb lsb 0 0 . . . 0 1 1 . . . 1 0 0 . . . 1 0 0 . . . 1 0 0 . . . 1 0 0 . . . 1 0 0 . . . 1 0 0 . . . 1 0 0 . . . 1 0 0 . . . 1 0 0 . . . 1 0 0 . . . 1 0 0 . . . 1 0 0 . . . 1 0 0 . . . 1 0 0 . . . 1 0 (note) 1 . . . 1 0 1 . . . 1 0 0.98 . . . 250 0 -0.98 . . . -250 note: power-on default value
m1008 preliminary cmos ic unisonic technologies co., ltd 8 of 11 www.unisonic.com.tw qw-r502-434.a ? timing diagrams
m1008 preliminary cmos ic unisonic technologies co., ltd 9 of 11 www.unisonic.com.tw qw-r502-434.a ? timing diagrams (cont.)
m1008 preliminary cmos ic unisonic technologies co., ltd 10 of 11 www.unisonic.com.tw qw-r502-434.a ? typical applications circuit cds mode 1 cdsclk1 2 cdsclk2 3 adcclk 4 oe 5 drvdd 6 drvss 7 d7(msb) 8 d6 9 d5 10 d4 11 d3 12 d2 13 d1 14 d0(lsb) 28 avdd 27 avss 26 vinr 25 offset 24 ving 23 cml 22 vinb 21 reft 20 refb 19 avss 18 avdd 17 sload 16 sclk 15 sdata p 5v/3v data outputs 5v 0.1f 0.1f 10f 0.1f 0.1f 5v 0.1f 0.1f 0.1f 1f 0.1f 0.1f 0.1f red input green input blue input cdsclk1 cdsclk2 adcclk sload sclk sdata m1008 sha mode
m1008 preliminary cmos ic unisonic technologies co., ltd 11 of 11 www.unisonic.com.tw qw-r502-434.a ? application considerations the digital outputs load should be minimized, either by using short traces to the digital asic, or by using external digital buffers. in order to minimize the number of code conversion in the main output of the impact of transients, which should happen in the coincidences cds clk2 falling on or before adcclk rising edge. all 0.1 f decoupling capacitor should be located as close as possible to the m1008 pins. when operating in a single channel mode, the unused analog inputs should be grounded. for the 3-channel sha mode, all of the above considerations also apply for th is configuration, except that the analog input signals are directly connected to the m1008 wi thout the use of coupling c apacitors. the offset pin should be grounded if the inputs to the m1008 are to be re ferenced to ground, or a dc offset voltage should be applied to the offset pin in the case where a coarse o ffset needs to be removed from the inputs. the analog input signals must already be dc-biased between 0v and 2v, if offset is connected to ground. utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.

▲Up To Search▲

Price & Availability of TSSOP-28

	To Download TSSOP-28 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .